1. Field of Invention
The present invention relates generally to a method and apparatus of a digital echo canceller. More particularly, the present invention relates to a method and apparatus of a digital echo canceller that only responds to echo signals to perform a multiplication-and-addition function.
2. Description of the Related Art
FIG. 1 illustrates a performance of a full-duplex digital transceiver. Both ends of the full-duplex digital transceiver are connected to a cable 22. Each end of the full-duplex digital transceiver has a transceiver 18 or 20. The transceiver 18 at the left end of the full-duplex digital transceiver comprises a transmitter (TX) 12, a receiver (RX) 14 and a hybrid circuit 16. The transmitter 12 and the receiver 14 are connected to the hybrid circuit 16 to receive and transmit signals.
If the transceiver 18 at the left end of the full-duplex digital transceiver is used as a near-end transceiver, the other transceiver at the right end will be a far-end transceiver. When the transmitter 12 transmits a signal to the far-end of the full-duplex digital transceiver 20, the transmitter will often not match the impedance of the far-end full-duplex digital transceiver 20 due to a transmitting cable 22. A far-end echo signal that will transmit to the near-end of the full-duplex digital transceiver 16 influences the received signal of the receiver 14. An interfering noise will occur.
To prevent the above-mentioned state from occurring, the conventional method will require designing a canceller to eliminate the echo signals. The structure illustrated in FIG. 2 is an adaptive finite impulse response digital echo canceller (adaptive FIR digital echo canceller). Xn signals are transmitted to a plurality of delay circuits D. After receiving the Xn signals, an output of each delay circuit D produces a signal. These signals are multiplied respectively to a plurality of significant coefficients C0, C1, C2, . . . CN−2, CN−1 to produce multiplied values. These multiplied values are then added together to produce a sum (the sum Σ is shown on the FIG. 2). An estimated echo signal is thus produced to eliminate the interference noise.
The above mentioned structure transmits signals utilizing a longer transmitting cable and a higher frequency (for example, a gigabit ethernet case, at the sample rate of 125 Mhz) to produce an echo signal's length that is shown in FIG. 3. The length of the echo signal is approximately 80 EC taps long. When the length of the echo signal is longer, the number of significant coefficients C0, C1, . . . CN−2, CN−1 that multiply respectively to the signals transmitted by the delay circuits D of FIG. 2 will increase. As a result, the amount of addition and multiplication operations that have to be calculated will also increase. The whole operation is not only complex, but the cost of the hardware is also high.